The present invention relates generally to design tools for application-specific integrated circuit integrated circuit (ASIC) design. More specifically, but without limitation thereto, the present invention relates to a method for characterizing a cell delay in a library format for integrated circuit design tools.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements connected together to perform a function. Cells are provided as part of an ASIC design technology library that defines which cells are implemented in a specific circuit design. The task of developing specific timing models for each cell in each technology may be expedited by utilizing a technology independent, cell functional description file format to describe families of circuits for standard software models, such as Verilog models. The standard software model is used in conjunction with technology dependent cell characterization and timing data by ASIC design tools to create a set of simulation models in the widely supported Verilog hardware description language (HDL). The Verilog models may then be distributed as part of an ASIC design system.
In the past, cell interconnect timing for application-specific integrated circuit (ASIC) design tools has been characterized as only a lumped capacitance load at the output. Because interconnect length was not significant in earlier technologies, it was not accounted for during cell timing characterization. Because cell timing model libraries only include cell timing, the interconnect timing must be computed externally, for example, by a delay calculator with asymptotic waveform evaluation (AWE), resulting in excessive run times.
Besides the cost in CPU time, current methods for characterizing cell interconnect delay for deep sub-micron technologies result in significant inaccuracy, because the cell delay is determined by the cell load rather than by the cell interconnect load.
The present invention advantageously addresses the problems above as well as other problems by providing a method for characterizing cell interconnect delay that may be included in a library for use with logic design tools.
In one embodiment, the present invention may be characterized as a method of characterizing cell interconnect delay that includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.
In another embodiment, the present invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform at least one of the following functions: (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs, and (c) generating a cell interconnect library comprising the calculated output ramptime and the total cell delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell.